Digital logic circuitry such as sequential logic circuits and combinatorial logic circuits implemented in contemporary integrated circuit short-scale CMOS processes suffers from leakage power losses. It is known to achieve power savings in such digital logic circuitry by utilizing so-called clock-gating mechanisms which save dynamic or switching power by preventing toggling regional clock signals of inactive circuit regions and leaf flip-flops.
Unfortunately, the digital logic circuitry of an inactive logic circuit region may still consume a relatively large amount of power due to respective leakage currents of the NMOS and PMOS transistors of digital logic circuits within the logic circuit region operated or controlled by the clock gating circuit. This leakage current is generally a growing problem with shrinking feature sizes of CMOS processes. The growing leakage current of NMOS and PMOS transistors is caused by subthreshold conduction and reverse biased diode leakage. This problem is particularly pronounced for digital logic circuitry operating at relatively low clock frequencies—for example with a clock frequency of less than 50 MHz or 25 MHz. The leakage power may exceed the dynamic power in certain digital logic circuitry operating at such relatively low clock frequencies. Integrated circuits for hearing instruments are one type of application where digital logic circuitry may be operating at these relatively low clock frequencies due to the extremely limited energy storage of conventional hearing instrument batteries.